/***********************************************************
 *  File Name:  555.H
 *
 *  Version: V1.0
 *
 *  Requirements:
 *
 *
 *
 *  Description:
 *      This contains the PSC 555 hardware definitions.
 *
 *  History:
 *
 *      Original          30-JAN-2001        P. Ahearn-Heyse
 *
 *
 ***********************************************************/



/***********************************************************************=
****
 *  555 Register definitions
 =
************************************************************************=
***/

#define __IMB          0x00000000          /* Internal Memory Base
                                              =3D> Multiple of 4 MB */

/* Added these to be compatible with Diab compiler - PAH 1/22/01  */

#define _Asm __asm



/***********************************************************************
***
 *  Various Registers in 555 internal memory space=20
**************************************************************************/

#define SYPCR   *((REG32*)(__IMB+0x2FC004)) // System Prot. Control Reg.
#define TBSCR   *((REG16*)(__IMB+0x2FC200)) // Time Base Ctrl+Stat. Reg
#define RTCSC   *((REG16*)(__IMB+0x2FC220)) // Real-Time Clock Stat+Ctrl.
#define RTC     *((REG32*)(__IMB+0x2FC224)) // Real-Time Clock Register
#define PISCR   *((REG16*)(__IMB+0x2FC240)) // Periodic IRQ Stat+Ctrl.
#define SIPEND  *((REG16*)(__IMB+0x2FC010)) // SIU Interrupt Pending Register
#define SIMASK  *((REG16*)(__IMB+0x2FC014)) // SIU Interrupt Mask Register
#define    SILEVELBIT(level) (((level)>=3D7) ? 1 : (1 << ((7-(level))<<1)))
#define    SIIRQBIT(irq)                         (2 << ((7-(irq))<<1))

#define SIEL    *((REG16*)(__IMB+0x2FC018)) // SIU Interrupt Edge Level Reg.
#define    SIELBITS(el)                          (3 << ((7-(el))<<1))
#define    SIEDGEBIT(edge)                       (2 << ((7-(edge))<<1))
#define    SIWAKEBIT(lvl)                        (1 << ((7-(lvl))<<1))

#define SIVEC   *((REG8 *)(__IMB+0x2FC01C)) // SIU Interrupt Vector


#define OR0     *((REG32*)(__IMB+0x2FC104)) // Memory Controller Option Reg.0
#define OR1     *((REG32*)(__IMB+0x2FC10C)) // Memory Controller Option Reg.1
#define OR2     *((REG32*)(__IMB+0x2FC114)) // Memory Controller Option Reg.2
#define OR3     *((REG32*)(__IMB+0x2FC11C)) // Memory Controller Option Reg.3
#define BR0     *((REG32*)(__IMB+0x2FC100)) // Memory Controller Base Reg.0
#define BR1     *((REG32*)(__IMB+0x2FC108)) // Memory Controller Base Reg.1=20
#define BR2     *((REG32*)(__IMB+0x2FC110)) // Memory Controller Base Reg.2=20
#define BR3     *((REG32*)(__IMB+0x2FC118)) // Memory Controller Base Reg.3
#define DMBR    *((REG32*)(__IMB+0x2FC140)) // Dual Mapping Base Register
#define DMOR    *((REG32*)(__IMB+0x2FC144)) // Dual Mapping Option Reg.
#define PLPRCR  *((REG32*)(__IMB+0x2FC284)) // PLL, Low-Power, and Reset-Ctrl.Reg.
#define SCCR    *((REG32*)(__IMB+0x2FC280)) // System Clock Control Register
#define MSTAT   *((REG32*)(__IMB+0x2FC178)) // Memory Controller Status Register
#define RAMBAR  *((REG16*)(__IMB+0x300004)) // RAM Array Base Adr. Reg.
#define UMCR    *((REG32*)(__IMB+0x307F80)) // UIMB Module Config. Register

#define TBSCRK  *((REG32*)(__IMB+0x2FC300)) // Time Base Status and Control Key
#define TBREF0K *((REG32*)(__IMB+0x2FC304)) // Time Base Reference 0 Key
#define TBREF1K *((REG32*)(__IMB+0x2FC308)) // Time Base Reference 1 Key
#define RTCSCK  *((REG32*)(__IMB+0x2FC320)) // Real Time Clock Status and Ctrl Key
#define RTCK    *((REG32*)(__IMB+0x2FC324)) // Real Time Clock Key
#define RTSECK  *((REG32*)(__IMB+0x2FC328)) // Real Time Alarm Seconds Key
#define RTCALK  *((REG32*)(__IMB+0x2FC32C)) // Real Time Alarm Key
#define PISCRK  *((REG32*)(__IMB+0x2FC340)) // PIT Status and Control Key
#define PITCK   *((REG32*)(__IMB+0x2FC344)) // PIT Count Key
#define SCCRK   *((REG32*)(__IMB+0x2FC380)) // System Clock Control Key
#define PLPRCRK *((REG32*)(__IMB+0x2FC384)) // PLL Low-Power and Reset-Ctrl Reg Key
#define RSRK    *((REG32*)(__IMB+0x2FC388)) // Reset Status Register Key
#define TBK     *((REG32*)(__IMB+0x2FC30C)) // Time Base and Decrementer Key





#define MIOS1MCR    *((REG16*)(__IMB+0x306806)) // MIOS1 Module Configuration Register

#define MIOS1LVL0   *((REG16*)(__IMB+0x306830)) // MIOS1 Interrupt Level Register 0
#define MIOS1LVL1   *((REG16*)(__IMB+0x306870)) // MIOS1 Interrupt Level Register 1
