From r.caldbeck@hs.utc.com Fri Jul  6 16:34 EDT 2001
From: "Caldbeck, Richard E. Jr.   HS" <r.caldbeck@hs.utc.com>
To: "'devans@virginia.edu'" <devans@virginia.edu>
Subject: RE: lclint bug report
Date: Fri, 6 Jul 2001 16:15:18 -0400 
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dave,

here you go -- i'll send 'em all as attachments with this email.

i've gotten the same error several times with various .c files.  in all
cases, it does this same error on the ending brace "}" of a function (but
not all functions cause this error!).

the following line gave me the errors (and removal of any parameters will
still produce the same error):

C:\> lclint avicreceivepackager.c -booltype BOOL -duplicatequals
-exportlocal

FILES:
   555.H
   AVICDriver.h
   AVICReceivePackager.c
   AVICReceivePackager.h
   m_qsmcm.h
   system.h


thanks!
Rick.


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Content-Type: application/octet-stream;
	name="system.h"
Content-Disposition: attachment;
	filename="system.h"

/***********************************************************
 *  File Name:  SYSTEM.H
 *
 *  Version: V1.0
 *
 *  Requirements:
 *
 *
 *
 *  Description:
 *      This contains the PSC system definitions.
 *
 *  History:
 *
 *      Original          30-JAN-2001        P. Ahearn-Heyse
 *
 *
 ***********************************************************/

#ifndef _SYSTEM_H
#define _SYSTEM_H





#ifdef DEBUG
   #define DEBUGMSG(cond,printf_exp) ((void)((cond)?(printf printf_exp),1:0))
   #define PSC_ERROR(printf_exp)     (printf printf_exp)

   #define DBG_INIT    1
   #define DBG_CONFIG  1
   #define DBG_READ    1
   #define DBG_WRITE   1
   #define DBG_ERROR   1
   #define DBG_TRACE   1
#else
   #define DEBUGMSG(cond,printf_exp) ((void)0)
   #define PSC_ERROR(printf_exp)     ((void)0)

   #define DBG_INIT    0
   #define DBG_CONFIG  0
   #define DBG_READ    0
   #define DBG_WRITE   0
   #define DBG_ERROR   0
   #define DBG_TRACE   0
#endif




/**************************************************************************
 *  Elementary defines and typedefs
 **************************************************************************/
typedef enum boolean_value_enum {FALSE=0, TRUE=1} BOOL;

#ifndef VOLATILE
   #define VOLATILE volatile            /* Compiler specific keyword */
#endif

#ifndef BYTE
typedef unsigned char BYTE;
#endif

/* The following are also defined by nucleus.h */
#ifndef NUCLEUS
typedef signed char INT8;
typedef unsigned char UINT8;
typedef signed short INT16;
typedef unsigned short UINT16;
typedef signed int INT32;
typedef unsigned int UINT32;
#endif

typedef VOLATILE signed char VINT8;
typedef VOLATILE unsigned char VUINT8;
typedef VOLATILE signed short VINT16;
typedef VOLATILE unsigned short VUINT16;
typedef VOLATILE signed int VINT32;
typedef VOLATILE unsigned int VUINT32;

typedef float FLOAT32;
typedef double FLOAT64;
typedef signed long long INT64;
typedef unsigned long long UINT64;
typedef VOLATILE signed long long VINT64;
typedef VOLATILE unsigned long long VUINT64;


typedef VOLATILE UINT32 REG32;
typedef VOLATILE UINT16 REG16;
typedef VOLATILE UINT8 REG8;


#ifndef INTERRUPT
   #define INTERRUPT __interrupt__      /* Compiler-specific keyword */
//   typedef INTERRUPT void (* _ExceptionHandler)(void);
   typedef void (* _IrqHandler)(void);
#endif

#ifndef REGISTER
   #define REGISTER register
#endif



#ifndef NULL
   #define NULL ((void *)0L)
#endif



/**************************************************************************
 *  PSC defines & typedefs
 **************************************************************************/

typedef UINT32 PSCStatusType;


#define PSC_OK            0
#define PSC_FAIL          0x7FFFFFFF

#define PSC_WRONGARG      1
#define PSC_BUSY          2
#define PSC_OVERRUN       3
#define PSC_NOTSUPPORTED  4
#define PSC_EMPTY         5




#define WORDMASK_BYTE1 0xFF000000
#define WORDMASK_BYTE2 0xFF0000
#define WORDMASK_BYTE3 0xFF00
#define WORDMASK_BYTE4 0xFF

 
extern const UINT32 WordBitMaskTable[];
extern const UINT16 ShortBitMaskTable[];
extern const UINT8 ByteBitMaskTable[];


typedef enum {IO_INPUT=0, IO_OUTPUT=1} IOModeType;

typedef enum {PSC_INVALID=0,PSC1, PSC2,PSC3} PSCIDType;
typedef enum {NOT_AVAILABLE=0, AVAILABLE=1} AvailableType;

#endif
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Content-Type: application/octet-stream;
	name="m_qsmcm.h"
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Content-Disposition: attachment;
	filename="m_qsmcm.h"

#ifndef _MPC555_QSMCM_H
#define _MPC555_QSMCM_H

#include "system.h"
#include "555.h"

#ifdef  __cplusplus
extern "C" {
#endif

/***********************************************************************=
*****/
/*                              MODULE :QSMCM                           =
    */
/***********************************************************************=
*****/
typedef struct QSMCM_tag {
    union {
        VUINT16 R;
        struct {
            VUINT16 STOP:1;
            VUINT16 FRZ1:1;
              VUINT16:6;
            VUINT16 SUPV:1;
              VUINT16:3;
            VUINT16 IARB:4;
        } B;
    } QSMCR;

    union {
        VUINT16 R;
        VUINT16 B;
    } QTEST;

    union {
        VUINT16 R;
        struct {
              VUINT16:3;
            VUINT16 ILDSCI:5;
              VUINT16:8;
        } B;
    } QDSCI_IL;

    union {
        VUINT16 R;
        struct {
              VUINT16:11;
            VUINT16 ILQSPI:5;
        } B;
    } QSPI_IL;

    union {
        VUINT16 R;
        struct {
            VUINT16 OTHR:1;
            VUINT16 LNKBD:1;
              VUINT16:1;
            VUINT16 SC1BR:13;
        } B;
    } SCC1R0;

    union {
        VUINT16 R;
        struct {
              VUINT16:1;
            VUINT16 LOOPS:1;
            VUINT16 WOMS:1;
            VUINT16 ILT:1;
            VUINT16 PT:1;
            VUINT16 PE:1;
            VUINT16 M:1;
            VUINT16 WAKE:1;
            VUINT16 TIE:1;
            VUINT16 TCIE:1;
            VUINT16 RIE:1;
            VUINT16 ILIE:1;
            VUINT16 TE:1;
            VUINT16 RE:1;
            VUINT16 RWU:1;
            VUINT16 SBK:1;
        } B;
    } SCC1R1;

    union {
        VUINT16 R;
        struct {
              VUINT16:7;
            VUINT16 TDRE:1;
            VUINT16 TC:1;
            VUINT16 RDRF:1;
            VUINT16 RAF:1;
            VUINT16 IDLE:1;
            VUINT16 OR:1;
            VUINT16 NF:1;
            VUINT16 FE:1;
            VUINT16 PF:1;
        } B;
    } SC1SR;

    union {
        VUINT16 R;
        struct {
              VUINT16:7;
            VUINT16 R8_T8:1;
            VUINT16 R7_T7:1;
            VUINT16 R6_T6:1;
            VUINT16 R5_T5:1;
            VUINT16 R4_T4:1;
            VUINT16 R3_T3:1;
            VUINT16 R2_T2:1;
            VUINT16 R1_T1:1;
            VUINT16 R0_T0:1;
        } B;
    } SC1DR;

    VUINT16 res22;
    VUINT16 res23;

    union {
        VUINT16 R;
        struct {
              VUINT16:4;
            VUINT16 QDRXD2:1;
            VUINT16 QDTXD2:1;
            VUINT16 QDRXD1:1;
            VUINT16 QDTXD1:1;
              VUINT16:1;
            VUINT16 QDPCS3:1;
            VUINT16 QDPCS2:1;
            VUINT16 QDPCS1:1;
            VUINT16 QDPCS0:1;
            VUINT16 QDSCK:1;
            VUINT16 QDMOSI:1;
            VUINT16 QDMISO:1;
        } B;
    } PORTQS;

    union {
        VUINT8 R;
        struct {
              VUINT8:1;
            VUINT8 QPAPCS3:1;
            VUINT8 QPAPCS2:1;
            VUINT8 QPAPCS1:1;
            VUINT8 QPAPCS0:1;
              VUINT8:1;
            VUINT8 QPAMOSI:1;
            VUINT8 QPAMISO:1;
        } B;
    } PQSPAR;

    union {
        VUINT8 R;
        struct {
              VUINT8:1;
            VUINT8 QDDPCS3:1;
            VUINT8 QDDPCS2:1;
            VUINT8 QDDPCS1:1;
            VUINT8 QDDPCS0:1;
            VUINT8 QDDSCK:1;
            VUINT8 QDDMOSI:1;
            VUINT8 QDDMISO:1;
        } B;
    } DDRQS;

    union {
        VUINT16 R;
        struct {
            VUINT16 MSTR:1;
            VUINT16 WOMQ:1;
            VUINT16 BITS:4;
            VUINT16 CPOL:1;
            VUINT16 CPHA:1;
            VUINT16 SPBR:8;
        } B;
    } SPCR0;

    union {
        VUINT16 R;
        struct {
            VUINT16 SPE:1;
            VUINT16 DSCKL:7;
            VUINT16 DTL:8;
        } B;
    } SPCR1;

    union {
        VUINT16 R;
        struct {
            VUINT16 SPIFIE:1;
            VUINT16 WREN:1;
            VUINT16 WRTO:1;
            VUINT16 ENDQP:5;
              VUINT16:3;
            VUINT16 NEWQP:5;
        } B;
    } SPCR2;

    union {
        VUINT8 R;
        struct {
              VUINT8:5;
            VUINT8 LOOPQ:1;
            VUINT8 HMIE:1;
            VUINT8 HALT:1;
        } B;
    } SPCR3;

    union {
        VUINT8 R;
        struct {
            VUINT8 SPIF:1;
            VUINT8 MODF:1;
            VUINT8 HALTA:1;
            VUINT8 CPTQP:5;
        } B;
    } SPSR;

    union {
        VUINT16 R;
        struct {
            VUINT16 OTHR:1;
            VUINT16 LNKBD:1;
              VUINT16:1;
            VUINT16 SC2BR:13;
        } B;
    } SCC2R0;

    union {
        VUINT16 R;
        struct {
              VUINT16:1;
            VUINT16 LOOPS:1;
            VUINT16 WOMS:1;
            VUINT16 ILT:1;
            VUINT16 PT:1;
            VUINT16 PE:1;
            VUINT16 M:1;
            VUINT16 WAKE:1;
            VUINT16 TIE:1;
            VUINT16 TCIE:1;
            VUINT16 RIE:1;
            VUINT16 ILIE:1;
            VUINT16 TE:1;
            VUINT16 RE:1;
            VUINT16 RWU:1;
            VUINT16 SBK:1;
        } B;
    } SCC2R1;

    union {
        VUINT16 R;
        struct {
              VUINT16:7;
            VUINT16 TDRE:1;
            VUINT16 TC:1;
            VUINT16 RDRF:1;
            VUINT16 RAF:1;
            VUINT16 IDLE:1;
            VUINT16 OR:1;
            VUINT16 NF:1;
            VUINT16 FE:1;
            VUINT16 PF:1;
        } B;
    } SC2SR;

    union {
        VUINT16 R;
        struct {
              VUINT16:7;
            VUINT16 R8_T8:1;
            VUINT16 R7_T7:1;
            VUINT16 R6_T6:1;
            VUINT16 R5_T5:1;
            VUINT16 R4_T4:1;
            VUINT16 R3_T3:1;
            VUINT16 R2_T2:1;
            VUINT16 R1_T1:1;
            VUINT16 R0_T0:1;
        } B;
    } SC2DR;

    union {
        VUINT16 R;
        struct {
            VUINT16 QTPNT:4;
            VUINT16 QTHFI:1;
            VUINT16 QBHFI:1;
            VUINT16 QTHEI:1;
            VUINT16 QBHEI:1;
              VUINT16:1;
            VUINT16 QTE:1;
            VUINT16 QRE:1;
            VUINT16 QTWE:1;
            VUINT16 QTSZ:4;
        } B;
    } QSCI1CR;

    union {
        VUINT16 R;
        struct {
              VUINT16:3;
            VUINT16 QOR:1;
            VUINT16 QTHF:1;
            VUINT16 QBHF:1;
            VUINT16 QTHE:1;
            VUINT16 QBHE:1;
            VUINT16 QRPNT:4;
            VUINT16 QPEND:4;
        } B;
    } QSCI1SR;

    union {
        VUINT16 R;
        VUINT16 B;
    } SCTQ[16];

    union {
        VUINT16 R;
        VUINT16 B;
    } SCRQ[16];

    VUINT16 RES25[106];

    union {
        VUINT16 R;
        VUINT16 B;
    } RECRAM[32];

    union {
        VUINT16 R;
        VUINT16 B;
    } TRANRAM[32];

    union {
        VUINT8 R;
        struct {
            VUINT8 CONT:1;
            VUINT8 BITSE:1;
            VUINT8 DT:1;
            VUINT8 DSCK:1;
            VUINT8 PCS3:1;
            VUINT8 PCS2:1;
            VUINT8 PCS1:1;
            VUINT8 PCS0:1;
        } B;
    } COMDRAM[32];
} QSMCM;


#define SCI  (*( struct QSMCM_tag *)  (__IMB + 0x305000))
//#define SCI_1  (*(__IMB + 0x305008))
//#define SCI_2  (*(__IMB + 0x305020))


#ifdef  __cplusplus
}
#endif


#endif /* ifndef _MPC555_QSMCM_H  */
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Content-Type: application/octet-stream;
	name="AVICReceivePackager.h"
Content-Disposition: attachment;
	filename="AVICReceivePackager.h"

/************************************************************
 *  File Name:  AVICReceivePackager.h
 *
 *  Version: V1.0
 *
 *  Requirements:
 *      AVIC
 *
 *  Description:
 *      This file contains the AVIC Receive Packager definitions.
 *
 *  History:
 *
 *      Original          24-MAY-2001        R. Caldbeck
 *
 *
 ************************************************************/


#ifndef _AVICRECEIVEPACKAGER_H
#define _AVICRECEIVEPACKAGER_H

#include "system.h"
#include "AVICDriver.h"


#define MSIZE 76                /* Message size, in bytes */

typedef struct {
    UINT16 last;                /* Pointer to last-used byte in msg */
    UINT8  msg[MSIZE];          /* Latest complete message */
    UINT8  AVIC_Receive_Status; /* ACK = valid message received
                                   NAK = no valid message received
                                   NOR = no response */
    UINT8  AVIC_Handshake_Rcv;  /* the ACK/NAK byte in msg[] */
} AVICReceivePackagerType;

extern AVICReceivePackagerType AVICReceivePackager1;
extern AVICReceivePackagerType AVICReceivePackager2;


extern const UINT8 NOR;     /* NOR = 0x00 */
extern const UINT8 ACK;     /* ACK = 0x06 */
extern const UINT8 NAK;     /* NAK = 0x15 */


void AVICReceivePackager_Initialize (void);
BOOL AVICReceivePackager_UnpackNewMessages
                (AVICDriverReceiveQueueStruct * const RXbuff);


#endif /* ifndef _AVICRECEIVEPACKAGER_H */
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Content-Type: application/octet-stream;
	name="AVICReceivePackager.c"
Content-Transfer-Encoding: quoted-printable
Content-Disposition: attachment;
	filename="AVICReceivePackager.c"

/************************************************************
 *  File Name:  AVICReceivePackager.c
 *
 *  Version: V1.0
 *
 *  Requirements:
 *      AVIC
 *
 *  Description:
 *      This file contains the AVIC Receive Packager functions.
 *
 *  History:
 *
 *      Original          24-MAY-2001        R. Caldbeck
 *
 *
 ************************************************************/

#include "AVICReceivePackager.h"


/* The "TIMEMOD" constant should be a value that, when multiplied
   by the RTC-difference between time2 and time1, results in a number
   of elapsed microseconds (usec) between the two RTC values.  This
   number is determined by the clock frequency and its pre-dividers. */

const FLOAT32 TIMEMOD =3D 1.0;

const UINT8 MAXCOUNT =3D (UINT8) (MSIZE - 4);

const UINT8 STX =3D (UINT8) 0x02;
const UINT8 ETX =3D (UINT8) 0x03;

const UINT8 NOR =3D (UINT8) 0x00;
const UINT8 ACK =3D (UINT8) 0x06;
const UINT8 NAK =3D (UINT8) 0x15;

AVICReceivePackagerType AVICReceivePackager1;
AVICReceivePackagerType AVICReceivePackager2;


static FLOAT32 AVICReceivePackager_Timeusec
                (const UINT32 time1, const UINT32 time2);
static BOOL AVICReceivePackager_ProcessMessage
                (AVICDriverReceiveQueueStruct * const RXbuff);
static BOOL AVICReceivePackager_ValidateMessage
                (AVICReceivePackagerType * const Message);



/************************************************************
 *  Name:  AVICReceivePackager_Initialize
 *
 *  Description:
 *      Initialize the AVICReceivePackager struct as per
 *      the requirements.
 *  Inputs:
 *      None.
 *  Outputs:
 *      None.
 *  Constraints:
 *      None.
 ************************************************************/      =20


void AVICReceivePackager_Initialize (void)
{
    AVICReceivePackager1.AVIC_Receive_Status =3D ACK;
    AVICReceivePackager2.AVIC_Receive_Status =3D ACK;
}



/************************************************************
 *  Name:  AVICReceivePackager_UnpackNewMessages
 *
 *  Description:
 *      If there is a new, complete AVIC message in either
 *      AVIC_1 or AVIC_2, then unpack it/them into RAM and
 *      process the messages (i.e. set flags, etc.).
 *  Inputs:
 *      None.
 *  Outputs:
 *      BOOL - is there a new, valid AVIC message?
 *  Constraints:
 *      None.
 ************************************************************/      =20


BOOL AVICReceivePackager_UnpackNewMessages
                (AVICDriverReceiveQueueStruct * const RXbuff)
{
    UINT32 time1;       /* RTC time of last-checked received AVIC byte =
*/
    UINT32 time2;       /* RTC time of AVIC byte currently being =
checked */
    UINT16 qptr;        /* Queue position pointer of byte being checked =
*/
    UINT16 qstop;       /* Queue position pointer of last received byte =
*/
    BOOL silence =3D FALSE;   /* STX with 5 msec of silence? */
    FLOAT32 timediff;   /* RTC time difference between prev & current =
byte */


    qptr =3D RXbuff->first;
    qstop =3D RXbuff->next;

    while (qptr !=3D qstop && silence =3D=3D FALSE)
    {
        /* Loop until start of new, valid AVIC message with no faults.. =
*/
        /* ..or until there are no more new received bytes to check. */

        if (RXbuff->queue[qptr] =3D=3D STX)
        {
            time1 =3D RXbuff->rtc[qptr !=3D 0 ? qptr-1 : QSIZE-1];
            time2 =3D RXbuff->rtc[qptr];
            timediff =3D AVICReceivePackager_Timeusec (time1, time2);

            if (timediff >=3D 5.0 && RXbuff->faults[qptr] =3D=3D =
(UINT8) 0)
                silence =3D TRUE;
            else
                silence =3D FALSE;
        }

        if (++qptr =3D=3D QSIZE)   /* check for wrap-around */
            qptr =3D 0;
    }

    /* At this point, qptr is either pointing just past the first byte
       of a new message (i.e. a no-fault ETX), or else it is pointing =
to
       qstop (i.e. no new message to process).  This means that there =
are
       no error-free ETX's preceded by 5 msec of silence.
       Once RXbuff->first is pointing to a no-fault ETX, it will stay
       there until the message is validated or terminated. */

    if (silence !=3D FALSE)
    {
        RXbuff->first =3D qptr - 1;
        return AVICReceivePackager_ProcessMessage (RXbuff);
    }
    else
    {
        RXbuff->first =3D qptr;
        if (RXbuff =3D=3D &AVICDriver_RXbuff1)
            AVICReceivePackager1.AVIC_Receive_Status =3D NOR;
        else
            AVICReceivePackager2.AVIC_Receive_Status =3D NOR;
        return FALSE;
    }
}



/************************************************************
 *  Name:  AVICReceivePackager_Timeusec
 *
 *  Description:
 *      Return a Float value that is the difference, in
 *      microseconds (usec), between the two time inputs.
 *  Inputs:
 *      time1 - older time (RTC value)
 *      time2 - newer time (RTC value)
 *  Outputs:
 *      FLOAT32 - difference in microseconds (usec)
 *                between time1 and time2.
 *  Constraints:
 *      The provided code inherently checks for wraparound.
 ************************************************************/      =20


static FLOAT32 AVICReceivePackager_Timeusec (const UINT32 time1,
                                             const UINT32 time2)
{
    return TIMEMOD * (FLOAT32) (time2 - time1);
}



/************************************************************
 *  Name:  AVICReceivePackager_ProcessMessage
 *
 *  Description:
 *      An ETX has been detected, so see if there is a complete
 *      message attached to it.  If so, then validate the message
 *      and, if it's good, save it.
 *  Inputs:
 *      RXbuff - An AVICDriverReceiveQueue (AVIC_1 or AVIC_2)
 *  Outputs:
 *      msg    - A complete, valid AVIC message.
 *      BOOL   - is there a new, valid AVIC message?
 *  Constraints:
 *      None.
 ************************************************************/      =20


static BOOL AVICReceivePackager_ProcessMessage
                (AVICDriverReceiveQueueStruct * const RXbuff)
{
    AVICReceivePackagerType *Message;   /* Pointer to Packager 1 or 2 =
*/
    UINT16 qptr;        /* Queue position pointer of byte being checked =
*/
    UINT16 qstop;       /* Queue position pointer of last received byte =
*/
    UINT16 msgptr =3D 0;  /* Position pointer for message being stored =
*/


    if (RXbuff =3D=3D &AVICDriver_RXbuff1)
        Message =3D &AVICReceivePackager1;
    else
        Message =3D &AVICReceivePackager2;

    Message->last =3D 0;

    qptr =3D RXbuff->first;
    qstop =3D RXbuff->next;

    /* Copy bytes from receive queue until end is reached (i.e. ETX). =
*/
    /* If any of the bytes have an error, set flag and abort mission! =
*/

    while (qptr !=3D qstop && RXbuff->queue[qptr] !=3D ETX &&
                            RXbuff->faults[qptr] =3D=3D (UINT8) 0)
    {
        Message->msg[msgptr++] =3D RXbuff->queue[qptr];

        if (++qptr =3D=3D QSIZE)   /* check for wrap-around */
            qptr =3D 0;
    }

    /* If there was a fault, push RXbuff->first up past the fault. */
    if (RXbuff->faults[qptr] !=3D (UINT8) 0)
    {
        RXbuff->first =3D qptr + 1;
        Message->AVIC_Receive_Status =3D NAK;
        return FALSE;
    }

    /* Else, if an ETX was reached, then store the message and set
       RXbuff->first to be just past the ETX. */
    else if (RXbuff->queue[qptr] =3D=3D ETX)
    {
        RXbuff->first =3D qptr + 1;
        Message->msg[msgptr] =3D ETX;
        Message->last =3D msgptr;
        return AVICReceivePackager_ValidateMessage (Message);
    }

    /* Else, an ETX was not reached, so sit and wait 'til next time. */
    else
    {
        /* for reference: qptr =3D=3D qstop */
        Message->AVIC_Receive_Status =3D NAK;
        return FALSE;
    }
}


/************************************************************
 *  Name:  AVICReceivePackager_ValidateMessage
 *
 *  Description:
 *      Validate the message.  Check for valid header, data,
 *      checksum, and trailer.  Verify that character count
 *      is correct and check the ACK/NAK byte.
 *  Inputs:
 *      Message - Message structure for AVIC_1 or AVIC_2
 *  Outputs:
 *      BOOL - is the message valid?
 *  Constraints:
 *      None.
 ************************************************************/      =20


static BOOL AVICReceivePackager_ValidateMessage
                (AVICReceivePackagerType * const Message)
{
    UINT32 i;           /* loop counter for current Data byte */
    UINT32 count;       /* number of Data & Checksum bytes */

    union {             /* running 16-bit checksum */
        UINT16 hword;
        struct {
            UINT8 MSB;
            UINT8 LSB;
        } byte;
    } checksum;


/*  Message->msg[0] will always be "STX". */

/*  Message->msg[1] should be "character count".
    This is a binary number range 0..255, of which 0..72 shall be the
    valid range.  This byte shall specify the combined length of the
    Data and Checksum bytes in this message. */

    count =3D (UINT32) (Message->msg[1]);

    if (count > (UINT32) MAXCOUNT)
    {
        /* INVALID -- Character count too long! */
        Message->last =3D 0;
        Message->AVIC_Receive_Status =3D NAK;
        return FALSE;
    }

    if (count =3D=3D 0)
    {
        /* There are no data or checksum bytes -- only a handshake! */
        if ((Message->msg[2] !=3D ACK &&
             Message->msg[2] !=3D NAK) ||
            (Message->msg[3] !=3D ETX))
        {
            Message->last =3D 0;
            Message->AVIC_Receive_Status =3D NAK;
            return FALSE;
        }
        else
        {
            Message->AVIC_Handshake_Rcv =3D Message->msg[2];
            Message->AVIC_Receive_Status =3D ACK;
            return FALSE;   /* no info to process!  don't know what to =
do */
            /* return TRUE; */
        }
    }


    /* Loop through all the Data, then compare it with the Checksum.
       The Checksum is a 16-bit binary integer sum of the bytes in
       the Data portion of the message.  It is sent as LSB first,
       followed by the MSB. */

    /* count =3D 1..72; last two are 16-bit Checksum LSB, MSB. */

    checksum.hword =3D 0;

    for (i=3D2; i<count; i++)
        checksum.hword +=3D (UINT16) (Message->msg[i]);


    /* Verify Checksum values:
       Message->msg[count] is the LSB of Checksum.
       Message->msg[count+1] is the MSB of Checksum. */

    if (checksum.byte.LSB !=3D Message->msg[count] ||
        checksum.byte.MSB !=3D Message->msg[count+1])
    {
        Message->last =3D 0;
        Message->AVIC_Receive_Status =3D NAK;
        return FALSE;
    }


    /* Verify Trailer (ACK/NAK and ETX)
       Message->msg[count+2] is ACK (0x06) or NAK (0x15).
       Message->msg[count+3] is ETX (0x03). */

    if ((Message->msg[count+2] !=3D ACK &&
         Message->msg[count+2] !=3D NAK) ||
        (Message->msg[count+3] !=3D ETX))
    {
        Message->last =3D 0;
        Message->AVIC_Receive_Status =3D NAK;
        return FALSE;
    }
    else
    {
        Message->AVIC_Handshake_Rcv =3D Message->msg[count+2];
        Message->AVIC_Receive_Status =3D ACK;
        return TRUE;
    }
}
------_=_NextPart_000_01C10658.60787400
Content-Type: application/octet-stream;
	name="AVICDriver.h"
Content-Disposition: attachment;
	filename="AVICDriver.h"

/************************************************************
 *  File Name:  AVICDriver.h
 *
 *  Version: V1.0
 *
 *  Requirements:
 *      AVIC
 *
 *  Description:
 *      This file contains the AVIC Driver definitions.
 *
 *  History:
 *
 *      Original          24-MAY-2001        R. Caldbeck
 *
 *
 ************************************************************/


#ifndef _AVICDRIVER_H
#define _AVICDRIVER_H

#include "system.h"
#include "m_QSMCM.h"



#define QSM_BASE (0x305000)    /* QSM Base Address */
#define QSM_SCC1R1   (* (REG16 *) (QSM_BASE+0x0a))
#define QSM_SC1SR    (* (REG16 *) (QSM_BASE+0x0c))
#define QSM_SC1DR    (* (REG16 *) (QSM_BASE+0x0e))
#define QSM_SCC2R1   (* (REG16 *) (QSM_BASE+0x22))
#define QSM_SC2SR    (* (REG16 *) (QSM_BASE+0x24))
#define QSM_SC2DR    (* (REG16 *) (QSM_BASE+0x26))


#define QSIZE 200         /* Queue size, in bytes */

typedef struct {
    UINT16 first;         /* Queue pointer for start of unprocessed bytes */
    UINT16 next;          /* Queue pointer for storage of next rcv'd byte */
    UINT32 rtc[QSIZE];    /* Array of RTC (Real-time Clock) values */
    UINT8  faults[QSIZE]; /* Array of fault values (NF,FE,PF) */
    UINT8  queue[QSIZE];  /* Array of received bytes */
} AVICDriverReceiveQueueStruct;

typedef struct {
    UINT16 next;          /* Queue pointer for next byte to transmit */
    UINT16 last;          /* Queue pointer for last byte to transmit */
    UINT8  queue[QSIZE];  /* Array of bytes to transmit */
} AVICDriverTransmitQueueStruct;



/* TX/RX queue structures */
extern AVICDriverReceiveQueueStruct AVICDriver_RXbuff1;
extern AVICDriverReceiveQueueStruct AVICDriver_RXbuff2;
extern AVICDriverTransmitQueueStruct AVICDriver_TXbuff1;
extern AVICDriverTransmitQueueStruct AVICDriver_TXbuff2;


void AVICDriver_Initialize (QSMCM * const AVIC);


#endif /* ifndef _AVICDRIVER_H  */
------_=_NextPart_000_01C10658.60787400
Content-Type: application/octet-stream;
	name="555.H"
Content-Transfer-Encoding: quoted-printable
Content-Disposition: attachment;
	filename="555.H"

/***********************************************************
 *  File Name:  555.H
 *
 *  Version: V1.0
 *
 *  Requirements:
 *
 *
 *
 *  Description:
 *      This contains the PSC 555 hardware definitions.
 *
 *  History:
 *
 *      Original          30-JAN-2001        P. Ahearn-Heyse
 *
 *
 ***********************************************************/



/***********************************************************************=
****
 *  555 Register definitions
 =
************************************************************************=
***/

#define __IMB          0x00000000          /* Internal Memory Base
                                              =3D> Multiple of 4 MB */

/* Added these to be compatible with Diab compiler - PAH 1/22/01  */

#define _Asm __asm



/***********************************************************************=
***
 *  Various Registers in 555 internal memory space=20
 =
************************************************************************=
**/

#define SYPCR   *((REG32*)(__IMB+0x2FC004)) // System Prot. Control =
Reg.
#define TBSCR   *((REG16*)(__IMB+0x2FC200)) // Time Base Ctrl+Stat. Reg
#define RTCSC   *((REG16*)(__IMB+0x2FC220)) // Real-Time Clock =
Stat+Ctrl.
#define RTC     *((REG32*)(__IMB+0x2FC224)) // Real-Time Clock Register
#define PISCR   *((REG16*)(__IMB+0x2FC240)) // Periodic IRQ Stat+Ctrl.
#define SIPEND  *((REG16*)(__IMB+0x2FC010)) // SIU Interrupt Pending =
Register
#define SIMASK  *((REG16*)(__IMB+0x2FC014)) // SIU Interrupt Mask =
Register
#define    SILEVELBIT(level) (((level)>=3D7) ? 1 : (1 << =
((7-(level))<<1)))
#define    SIIRQBIT(irq)                         (2 << ((7-(irq))<<1))

#define SIEL    *((REG16*)(__IMB+0x2FC018)) // SIU Interrupt Edge Level =
Reg.
#define    SIELBITS(el)                          (3 << ((7-(el))<<1))
#define    SIEDGEBIT(edge)                       (2 << ((7-(edge))<<1))
#define    SIWAKEBIT(lvl)                        (1 << ((7-(lvl))<<1))

#define SIVEC   *((REG8 *)(__IMB+0x2FC01C)) // SIU Interrupt Vector


#define OR0     *((REG32*)(__IMB+0x2FC104)) // Memory Controller Option =
Reg.0
#define OR1     *((REG32*)(__IMB+0x2FC10C)) // Memory Controller Option =
Reg.1
#define OR2     *((REG32*)(__IMB+0x2FC114)) // Memory Controller Option =
Reg.2
#define OR3     *((REG32*)(__IMB+0x2FC11C)) // Memory Controller Option =
Reg.3
#define BR0     *((REG32*)(__IMB+0x2FC100)) // Memory Controller Base =
Reg.0
#define BR1     *((REG32*)(__IMB+0x2FC108)) // Memory Controller Base =
Reg.1=20
#define BR2     *((REG32*)(__IMB+0x2FC110)) // Memory Controller Base =
Reg.2=20
#define BR3     *((REG32*)(__IMB+0x2FC118)) // Memory Controller Base =
Reg.3
#define DMBR    *((REG32*)(__IMB+0x2FC140)) // Dual Mapping Base =
Register
#define DMOR    *((REG32*)(__IMB+0x2FC144)) // Dual Mapping Option Reg.
#define PLPRCR  *((REG32*)(__IMB+0x2FC284)) // PLL, Low-Power, and =
Reset-Ctrl.Reg.
#define SCCR    *((REG32*)(__IMB+0x2FC280)) // System Clock Control =
Register
#define MSTAT   *((REG32*)(__IMB+0x2FC178)) // Memory Controller Status =
Register
#define RAMBAR  *((REG16*)(__IMB+0x300004)) // RAM Array Base Adr. Reg.
#define UMCR    *((REG32*)(__IMB+0x307F80)) // UIMB Module Config. =
Register

#define TBSCRK  *((REG32*)(__IMB+0x2FC300)) // Time Base Status and =
Control Key
#define TBREF0K *((REG32*)(__IMB+0x2FC304)) // Time Base Reference 0 =
Key
#define TBREF1K *((REG32*)(__IMB+0x2FC308)) // Time Base Reference 1 =
Key
#define RTCSCK  *((REG32*)(__IMB+0x2FC320)) // Real Time Clock Status =
and Ctrl Key
#define RTCK    *((REG32*)(__IMB+0x2FC324)) // Real Time Clock Key
#define RTSECK  *((REG32*)(__IMB+0x2FC328)) // Real Time Alarm Seconds =
Key
#define RTCALK  *((REG32*)(__IMB+0x2FC32C)) // Real Time Alarm Key
#define PISCRK  *((REG32*)(__IMB+0x2FC340)) // PIT Status and Control =
Key
#define PITCK   *((REG32*)(__IMB+0x2FC344)) // PIT Count Key
#define SCCRK   *((REG32*)(__IMB+0x2FC380)) // System Clock Control Key
#define PLPRCRK *((REG32*)(__IMB+0x2FC384)) // PLL Low-Power and =
Reset-Ctrl Reg Key
#define RSRK    *((REG32*)(__IMB+0x2FC388)) // Reset Status Register =
Key
#define TBK     *((REG32*)(__IMB+0x2FC30C)) // Time Base and =
Decrementer Key





#define MIOS1MCR    *((REG16*)(__IMB+0x306806)) // MIOS1 Module =
Configuration Register

#define MIOS1LVL0   *((REG16*)(__IMB+0x306830)) // MIOS1 Interrupt =
Level Register 0
#define MIOS1LVL1   *((REG16*)(__IMB+0x306870)) // MIOS1 Interrupt =
Level Register 1

------_=_NextPart_000_01C10658.60787400--


